Metallization patterns on integrated circuits can be formed by depositing a dielectric layer, patterning the dielectric layer by photolithography and reactive ion etching to form grooves or trenches, and depositing a metal layer that fills the trenches in the dielectric layer. Typically, the metal layer not only fills the trenches but also covers the entire semiconductor wafer. The excess metal is then removed using, for example, chemical-mechanical polishing or an etchback process so that only the metal in the trenches remains. This process, called the “damascene process,” can be used to avoid at least some of the problems associated with metal etching, such as, for example, lack of suitable dry-etch plasma chemistries, problems in dimension control, the formation of small gaps that are difficult to fill with the subsequent dielectric layer, and the entrapment of impurities in the inter-wiring spaces. This process is disclosed in U.S. Pat. No. 4,944,836, to Beyer et al., the entire disclosure of which is incorporated herein by reference. See also U.S. Pat. No. 4,789,648, to Chow et al., the entire disclosure of which is incorporated herein by reference.
Cu interconnects are finding increasing application in electronic devices, such as integrated circuits. The use of Cu and Cu alloys in such applications can result in several advantages over the use of aluminum and its related alloys, which have been conventionally used as chip interconnection materials. These advantages can include, for example, reduced resistivity, greater reliability, high chip yield count, and higher circuit density. Cu can also have use in interconnects made by the damascene process. For example, Cu damascene interconnects have been found to be useful in very large scale integrated (VLSI) circuits and ultra large scale integrated (ULSI) circuits. See, for example, Edelstein, et al., “Full Copper Wiring in a Sub-0.25 mm CMOS ULSI Technology”, Tech. Dig. IEEE IEDM (International Electron Devices Meeting), 376, (1997).
However, since copper has a tendency when used in interconnect metallurgy to diffuse into surrounding dielectric materials such as silicon dioxide, encapsulation of the copper is often desirable. One method of capping includes employing a conductive liner or barrier layer along the sidewalls and bottom surface of a copper interconnect. Alpha-phase tantalum (α-Ta) is often used as such a liner material due to its effectiveness as a Cu diffusion barrier, relatively easy integration, and good electrical conductivity. See, for example, Edelstein, et al., “A High Performance Liner for Copper Damascene Interconnects”, Digest of Technical Papers, IEEE IITC (International Interconnect Technology Conference), pp. 9–11 (2001); see also U.S. Pat. Nos. 5,221,449 and 5,281,485 to Colgan, et al. and U.S. Pat. Nos. 6,437,440 and 6,291,885 to Cabral, Jr., et al. Tantalum nitride (TaN), which has relatively higher resistivity, can also be used as a liner material. Bilayer TaN/Ta, in particular, has been employed as a liner for Cu interconnects as it exploits the best properties of both films. In addition, it exploits the phenomenon exhibited by TaN to promote the formation of α-Ta when Ta is deposited on top of TaN.
The reliability of both aluminum and copper-based interconnections in electronic circuits can be limited by a phenomenon known as electromigration (EM). In one mechanism of EM, aluminum or copper electromigrates away from a cathode region in the interconnection faster than the availability of additional atoms can take its place. This process generates a void in the interconnection. Growth of this void increases the electrical resistance of the interconnection to a point where circuit failure eventually occurs. One means of alleviating the effects of electromigration involves utilization of an electrically redundant layer, which can provide a secondary conductor in the event that a void is formed in the interconnection. See, for example, Edelstein, et al., “An Optimal Liner for Copper Damascene Interconnects,” AMC 2002 (Advanced Metallization Conference 2002), published by Mat. Res. Soc., Warrendale, Pa., 541 (2002).
Since α-Ta is often used as a liner material for Cu interconnects and has relatively good conductivity, it can also be used as a redundant layer in which it can assist the main copper conductor in current distribution as well as become the main conductor in the event the copper fails due to phenomena such as electromigration.
While TaN/α-Ta has been shown to serve adequately a dual purpose as both a barrier layer and a redundant layer for use in Cu interconnects, studies of its use as a secondary conductor in the event of Cu void formation as the result of EM stress have only been recently reported. See, Li, et al., “Line Depletion Electromigration Characteristics of Cu Interconnects”, IRPS 2003 (International Reliability Physics Symposium 2003).